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SX1210
ADVANCED COMMUNICATIONS & SENSING
5.4. Buffered Mode
5.4.1. General Description
As illustrated in Figure 30, for Buffered mode operation the NRZ data from the demodulator is not directly accessed
by the uC but stored in the FIFO and accessed via the SPI Data interface. This frees the uC for other tasks
between processing data from the SX1210, furthermore it simplifies software development and reduces uC
performance requirements (speed, reactivity). Note that in this mode the packet handler stays inactive.
An important feature is also the ability to empty the FIFO in Stby mode, ensuring low power consumption and
adding greater software flexibility.
SX1210
CONTROL
IRQ_0
IRQ_1
Data
Rx
SYNC
RECOG.
SPI
CONFIG
NSS_CONFIG
FIFO
(+SR)
NSS_DATA
DATA
SCK
MOSI
MISO
Datapath
Figure 30: Buffered Mode Conceptual View
Note that Bit Synchronizer is automatically enabled in Buffered mode. The Sync word recognition must be enabled
(RXParam_Sync_on=1) independently of the FIFO filling method selected (IRQParam_Fifo_fill_method).
5.4.2. Rx Processing
After entering Rx in Buffered mode, the chip requires the uC to retrieve the received data from the FIFO. The FIFO
will actually start being filled with received bytes either; when a Sync word has been detected (in this case only the
bytes following the Sync word are filled into the FIFO) or when the Fifo_fill bit is asserted by the user - depending
on the state of bit, IRQParam_Fifo_fill_method.
In Buffered mode, the packet length is not limited i.e. as long as Fifo_fill is set, the received bytes are shifted into
the FIFO.
The uC software must therefore manage the transfer of the FIFO contents by interrupt and ensure reception of the
correct number of bytes. (In this mode, even if the remote transmitter has stopped, the demodulator will output
random bits from noise)
Rev 2– Sept 8 , 2008
th
Page 38 of 73
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